The present disclosure relates generally to the field of integrated circuit designs and performance, and more particularly to determining intra-die variation of an integrated circuit. Across chip variation (hereinafter “ACV”) describes how two or more transistors or identical circuits behave on a given die or microchip (hereinafter “chip”). A die is a small block of semiconducting material on which a circuit is fabricated. ACV in a chip may present in one of two forms, systematic or random. Systematic ACV refers to the portion of ACV that is correlated to variations in specific electrical and/or physical parameters such as transistor threshold voltage or gate oxide thickness and is typically spatially correlated across the chip. Random ACV refers to the portion of ACV that is statistically independent of any known electrical of physical parameter and is typically not spatially correlated across the chip.
Chip manufacturing typically requires the use of semiconductor materials, dopants, metals, and insulators. Chips are fabricated in a layer process which includes imaging, deposition, and etching, all of which are typically supplemented by doping and cleaning. Mono-crystal silicon wafers are commonly used as the substrate. A wafer typically undergoes testing before being sent to die preparation, wherein all individual ICs present on the wafer are tested for functional defects and power-performance. One of the phenomena analyzed during testing is ACV, wherein an IC fails testing if its electrical characteristics are below or above a certain threshold. In addition to systematic ACV, an IC's electrical characteristics are also affected by a local region of influence effect, which describes the influence of the surrounding electrical structures on a particular circuit within the IC.